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Yixiao Du

Ph.D. student at Cornell University

About Me

Thanks for visiting my website! I am an MS/PhD student at Cornell ECE, working in Computer Systems Lab under the supervision of Prof. Zhiru Zhang. My current research focuses on designing flexible and efficient accelerators for sparse workloads (e.g, sparse matrix multiply, graph analytics), while I am also interested in high-level synthesis (HLS) and design automation. I am familiar RTL and HLS design flows, and have rich experience in FPGA prototyping and testing.

Education

MS/Ph.D. in Electrical and Computer Engineering

August 2020 - Present
Cornell University

M.Eng. in Electrical and Computer Engineering

August 2019 - August 2020
Cornell University

Transferred to MS/Ph.D. program in August 2020
GPA: 4.04/4.25

B.Eng. in Microelectronics Science and Engineering

September 2015 - June 2019
University of Electronics Science and Technology of China

GPA: 3.91/4.00

Experiences

Research Intern

May 2023 - December 2023
Mangoboost Inc., Bellevue, WA
  • Built testing hardware in Verilog to characterize the high-bandwidth memory (HBM) system on AMD Alveo U55C FPGA.
  • Explored functional simulation of HLS designs interfacing with NVMe.

Honors & Awards

ECE Outstanding Ph.D. Teaching Assistant Award

April 2023
Awarded by School of Electrical and Computer Engineering, Cornell University

Only one winner per year with a $3000 prize

Open-Source Projects

HiSparse - An SpMV accelerator in HLS for HBM-equipped FPGAs
GraphLily - An FPGA overlay for graph linear algebra
svpp - Mixing HLS and backend versions in Vitis

Publications

  • Vesper: A Versatile Sparse Linear Algebra Accelerator With Configurable Compute Patterns
    • Hanchen Jin, Zichao Yue, Zhongyuan Zhao, Yixiao Du, Chenhui Deng, Nitis Srivastava, Zhiru Zhang
    IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), November 2024
  • Rapid GPU-Based Pangenome Graph Layout
    • Jiajie Li, Jan-Niklas Schmelzle, Yixiao Du, Simon Heumos, Andrea Guarracino, Giulia Guidi, Pjotr Prins, Erik Garrison, Zhiru Zhang
    International Conference for High Performance Computing, Networking, Storage, and Analysis (SC), November 2024
  • Understanding the Potential of FPGA-Based Spatial Acceleration for Large Language Model Inference
    • Hongzheng Chen, Jiahao Zhang, Yixiao Du, Shaojie Xiang, Zichao Yue, Niansong Zhang, Yaohui Cai, Zhiru Zhang
    ACM Transactions on Reconfigurable Technology and Systems (TRETS), March 2024
  • High-Performance Sparse Linear Algebra on HBM-Equipped FPGAs Using HLS: A Case Study on SpMV
    • Yixiao Du, Yuwei Hu, Zhongchun Zhou, Zhiru Zhang
    International Symposium on Field-Programmanle Gate Arrays (FPGA), February 2022
  • GraphLily: Accelerating Graph Linear Algebra on HBM-Equipped FPGAs
    • Yuwei Hu, Yixiao Du, Ecenur Ustun, Zhiru Zhang
    International Conference on Computer-Aided Design (ICCAD), November 2021

    Skills

    Verilog/System Verilog

    Vitis HLS

    Catapult HLS

    Vivado

    Python

    C/C++

    Cadence Virtuoso